In fabrication of bipolar transistors for silicon integrated circuits, formation of both the base and emitter electrodes from polysilicon allows for reduced collector-base overlap area, and reduces collector-base parasitic capacitances.
In known processes for formation of a polysilicon emitter structure for a bipolar transistor, the process steps typically involve formation of a device well in a silicon semiconductor substrate, and formation of an intrinsic base region therein; deposition of first layer of polysilicon (base poly) to form extrinsic base contact electrodes; patterning and opening of an emitter window in the first (base) polysilicon layer; forming local isolation in the form of sidewall spacers within the opening; and, formation of a second polysilicon layer within the emitter window to form an emitter structure.
However, there are several problems in this approach. First, the step of photolithographic patterning and etching the emitter window in polysilicon material deposited on a single crystal silicon substrate results in etch damage to the exposed device well region when the substrate is over-etched, because the etch rate of polysilicon relative to crystalline in known etch processes is comparable. Thus etching of polysilicon on a crystalline silicon substrate is not highly selective. Since some overetching of the substrate is practically unavoidable to provide a manufacturable process, the resulting etch damage to the silicon of the substrate contributes to degraded device performance. Second, two masking layers are required to define the emitter structure, one for patterning the emitter window and one for defining the polysilicon emitter structure. Further masking steps may be required for defining an area of increased doping in the base contact area, to reduce base contact resistance. Additionally, the resulting topography is highly non-planar, which complicates subsequent photoengraving and metallization steps for providing contacts to the base and emitter electrodes.
A number of schemes have been proposed to alleviate these problems. For example, as described in an article by J. H. Comfort et al., entitled "Profile leverage in a self-aligned epitaxial Si or SiGe Base Bipolar Technology" 1990 IEEE IEDM 90-21, p. 2.4.1, and another article by E. Ganin et al., entitled "Epitaxial base, double poly self-aligned bipolar transistors", page 24.6.1 of the same reference, selective epitaxial overgrowth is used to form a self-aligned epitaxial base, either in an epitaxy-after-sidewall approach or an epitaxy-before-sidewall approach. Alternatively, selective epitaxy may be used in a self-aligned emitter to base process in which an emitter window is defined by using an in-situ doped epitaxial lateral overgrowth over a patterned thin oxide/nitride pad.
In another scheme, as described in an article entitled "A high speed bipolar LSI process using self-aligned double diffusion polysilicon technology", by K. Kikuchi et al., IEDM abstracts p.420, 1986, a self-aligned process comprises masking the emitter diffusion window with a CVD oxide pattern before forming the first polysilicon base electrodes, then removing the oxide pattern and forming the emitter structure by deposition and patterning of a second polysilicon layer.
Another approach is described in U.S. Pat. No. 5,320,972 to Wylie entitled "Method of forming a bipolar transistor" which describes a self aligned single polysilicon bipolar transistor.
While other processes for formation of bipolar transistors are known, it is desirable for bipolar CMOS integrated circuits that a process for forming a bipolar transistor should be compatible with conventional known silicon technology for CMOS processes, so that optimal performance of both bipolar and CMOS devices can be achieved without unduly adding to the overall number of process steps and process complexity, and with a minimum number of additional mask levels.